Efficient Implementation of WiMAX Physical Layer on Multi-core Architectures with Dynamically Reconfigurable Processors

Abstract

Wireless internet access technologies have significant market
potential, especially the WiMAX protocol which can offer data rate
of tens of Mbps. A significant demand for embedded high performance
WiMAX solutions is forcing designers to seek single-chip
multiprocessor or multi-core systems that offer competitive
advantages in terms of all performance metrics, such as speed, power
and area. Through the provision of a degree of flexibility similar
to that of a DSP and performance and power consumption advantages
approaching that of an ASIC, emerging dynamically reconfigurable
processors are proving to be strong candidates for future high
performance multi-core processor systems. This paper presents
several new single-chip multi-core architectures, based on newly
emerging dynamically reconfigurable processor cores, for the WiMAX
physical layer. A simulation platform is proposed in order to
explore and implement various multi-core solutions combining
different memory architectures and task partitioning schemes. The
paper describes the architectures, the simulation environment,
several task partitioning methods and demonstrates that up to 4.9x
speedup can be achieved by employing five dynamically reconfigurable
processor cores each having individual local memory units.