Looking at the history of computing one can find out that the designers repeatedly addressed specialized (non von-Neumann) architectures which provide comparatively high performance in some specific applications. Suffice it to say that one of the earliest supercomputer projects, the S. Unger's system destined for pattern recognition was a rectangular array of interconnected simple processing modules.
At the beginning of 60s, an original conception of a reconfigurable cellular structure called Homogeneous Computing Medium was suggested in Russia. It is worth to note that recently this promising idea found its continuation in the MIT project Raw based on newest technology.
Great consideration was given to associative memories and fine-grained SIMD architectures. Thus, in the late 80s the massively parallel fine-grained systems DAP (S. Reddaway) and CM (D. Hillis) made at the market a grave competition to the supercomputers of conventional architecture.
In 90s, powerful microprocessors of essentially traditional architecture occupied the dominating position due to the rapid progress in microelectronics and the corresponding dramatic decrease of component cost.
Nevertheless, the well-known rule remains valid: taking into account specific features of a given class of problems and computational methods, one can get great improvement in performance and cost/performance factor when using application specific unconventional architectures.
After the publishing of the CFP for this Special Issue of SCPE, we received 10 papers submitted by 19 authors from various countries. In the present Issue five papers are being published which obtained the highest rating from reviewers. These papers introduce some interesting trends in the development of unconventional parallel computing systems.
The first paper Reaction-Diffusion and Excitable Processors: a Sense of Unconventional by Andrew Adamatzky is devoted to a very important and prospective subject of parallel data processing in chemical media. So-called architecture-less processors are discussed where a layer of an oscillating reaction is considered a massively parallel system each elementary processor of which is represented by a micro-volume reactor. Cellular automata are used as a computational model. The author demonstrates that excitable media can constitute universal massively parallel computing devices.
In the second paper A Scalable Multiprocessor for Real-Time Signal Processing Applications Hans Eberle and Daniel Scherrer present a new platform for real-time processing of continuous data streams such as audio, video or graphical data. To overcome the limitations of existing DSPs the authors designed a flexible and scalable communication infrastructure Switcherland which guarantees data transfer with bounded latencies. The advantages of suggested multiprocessor provide for a wide range of applications in real-time signal processing.
Bernard Girau in his paper Conciliating Connectionism and Parallel Digital Hardware presents an original paradigm of digital hardware implementation of neural computations, Field Programmable Neural Arrays (FPNAs). Both theoretical and practical aspects are discussed including the mapping of FPNAs into FPGAs. It is shown that the suggested FPNA framework results in efficient fine-grained reconfigurable parallel hardware.
Bertil Schmidt and Manfred Schimmler describe in their paper KPROC—an Instruction Systolic Architecture for Parallel Prefix Applications a highly parallel architecture with 1024 floating-point processors on a single chip (at 0.25 micron CMOS technology). These processors constitute an instruction systolic array implementing parallel prefix computation. It is shown that many important applications can take advantage of the suggested model. Examples are discussed from different areas such as image processing, long argument arithmetic, etc.
Finally, researchers from Computer Technology Institute (Patras, Greece) C. Konstantinopulos, A. Svolos, D. Serpanos, and D. Maritsas in the paper The Effect of Interword Connectivity in Associative Processing bring forward an important development of associative processors. They introduce an asssociative memory with a single-stage hypercube network interconnecting the memory words. Significant performance improvement of this architecture is demonstrated through the analysis of various real applications.
We wish to express our deep gratitude to the reviewers (D. Sima, F. Vajda, K. Grosspietsch, P. Szolgay, E. Luque, A. Pimentel, D. Ortega, M. Valero, O. Bandman, V. Malyugin, P. Keresztes, M. Amamiya, Y. Fet, R. Moore, K. Waldschmidt, S. Theodoridis, L. Ricci, A. Ripoll, S-W. Lee, J-L. Gaudiot, V. Estigneev, S. Sedukhin) who helped us to select the best papers and to improve the quality of the accepted.
Yakov Fet and Péter Kacsuk