High performance computing through SoC coprocessors

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Gianni Danese
Francesco Leporati
Marco Bera
Mauro Giachero
Nelson Nazzicari
Alvaro Spelgatti


In this paper we describe DPFPA (Double Precision Floating Point Accelerator),
a FPGA-based coprocessor interfaced to the CPU through standard bus
connections; it is conceived to accelerate double precision floating
point operations, featuring two double precision floating point units,
a pipelined adder and a pipelined multiplier with a suitable number
of stages. We tested its performance by implementing a Montecarlo-Metropolis
simulation of a dipolar system, using a proper software development
environment designed and realized in our laboratory. DPFPA can provide
a speed-up equal to 4, with respect last generation PC, showing also
a good scalability in terms of clock frequency, memory capability
and number of computing units.

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