Design and Development of Memory Pixel Architecture for Sobel Edge Detection

Abstract

Memory is a fundamental hardware structure used in various electronic and multi-media products. The design and development of large-size memory architectures have become increasingly complex due to the growing demands of high-resolution image processing applications. This research work aims to design a specialized memory architecture module for Sobel edge detection, an essential technique in image processing. The proposed architecture (memory pixel size) consists of memory unit, comprising rows and columns, is determined by the image resolution. For effective Sobel edge detection, the image pixels must be stored in memory, and read operations are performed to access a 3x3 matrix of nine pixels. A critical consideration in developing this memory architecture is power dissipation, which is mitigated through the application of Clock Gating techniques. The proposed pixel memory architecture is implemented using MATLAB and Xilinx ISE software with Verilog HDL. The image pixel memory is developed using Block RAMs (BRAMs) and registers, and the 3x3 pixel matrix required for the Sobel edge detector is generated. Simulation, synthesis, and power analysis are conducted for the image pixel memory across source images with various resolutions, including 10x40, 10x20, 128x128, 320x240, and 512x512. The results indicate reduced power dissipation from 30% to 40% due to Clock Gating. This work demonstrates the effectiveness of the proposed memory architecture in reducing power consumption while maintaining performance. Future work aims to further enhance the performance of image pixel memory by decreasing the number of registers and improving pixel access times. Such module will provide a more efficient and scalable solution for high-resolution image processing applications.